FIG. 1 includes a circuit diagram of a six-transistor static-random-access memory (SRAM) cell 300 that includes two access transistors 311 and 321, two latch transistors 312 and 322, and two load transistors 313 and 323. The access transistors 311 and 321 have first source/drain regions that are coupled to a bit line signal (BL) and a complementary bit line signal (BL), respectively. Source regions of the latch transistors 312 and 322 are coupled to V.sub.SS, and source regions of the load transistors are coupled to V.sub.DD. The SRAM cell 300 further includes a word line 301 coupled to the gate electrodes of the access transistors 311 and 321. A second source/drain region of the access transistor 311 and drain regions of the latch and load transistors 312 and 313 are electrically connected to one another to form a first storage node 310. A second source/drain region of the access transistor 321 and drain regions of the latch and load transistors 322 and 323 are electrically connected to one another to form a second storage node 320. The gate electrodes for the latch and load electrodes 312 and 313 are coupled to the second storage node 320, and the gate electrodes for the latch and load electrodes 322 and 323 are coupled to the first storage node 310. The pass and latch transistors 311, 321, 312, 322 are n-channel transistors, and the load transistors 313 and 323 are p-channel transistors.
As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory (DRAM) device or typical SRAM device, the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
One technique for reducing memory cell dimensions is to place a number of the components in a trench structure, which is sunk into the substrate. More specifically, a toroidal shared-gate SRAM cell may be formed. The SRAM cell includes vertical latch and load transistors that have active regions that lie along or within trenches. With respect to the latch transistors of the SRAM cell, the drain regions lie adjacent to the top of the trench, and the source regions lie adjacent to the bottom of the trench. The source regions are heavily n-type doped and are electrically isolated underneath by a lightly p-type doped layer. The combination of the active regions of the latch transistors and the lightly p-type doped layer forms an npnp structure and may be biased under certain conditions in such a way as to cause a latch-up condition to occur and is undesired.